|
Track 2 Session 1
9:10 to 10:10 a.m. Wednesday,
October 22, 2008
Supplier Quality and Reliability Development in
Integrated Circuit (IC) Packaging of Multi-layered Leadframes
Engineering processes and reliability techniques were implemented in the development of multi-layered leadframe for high-density leadless IC package platform. The important enablers will be identified and appropriate competencies were developed to provide compatibility between the leadframe supplier and the IC packaging assembly site. The supplier adjusted their current processes in their substrate manufacturing line to adapt to the quality and reliability requirements needed in the assembly of multi-layered leadframes. Different reliability tests were conducted according to the JEDEC standards and evaluation results will be presented. Monitoring results were also put in place to provide indicators of the process sustainability.
Key Words: Quality and Reliability Development, FMEA, JEDEC, Risk Assessment
Randolph E. Flauta
NXP Semiconductors |
|
|
|
|